The new Espressif ESP32-S3 dual core system-on-chip (SOC) now has applications in AIot.
Espressif Systems, in September 2020, announced that they were planning to release a new ESP-32 chip for AI instructions and multiple CPU cores, along with some more features. On the last day of the same year, the chip was finally launched and all of the details for the chip were also made public.
Some of those details included an updated dual core MCU for Wi-fi and BLE capabilities, expanded GPIO, AI-focused instructions and reliable security features among others.
The Espressif ESP32-S3 features a dual-core LX7 32-bit processor operating up to 240 MHz. (The previous -S2 was single-core.) On-chip is 512 KB of SRAM and 384 KB of RAM with support for octal SPI to connect to external memory devices. The RF capabilities include WiFi 2.4 GHz b/g/n, legacy Bluetooth, and Bluetooth Low-Energy 5.0.
ESP32-S3 Specifications:
CPU
- Dual-core Tensilica LX7 up to 240 MHz with additional vector instructions for AI acceleration
- ULP core to handle low power modes
- Memory – 512 KB of internal SRAM
- Storage – Octal SPI flash and PSRAM support (supports larger, high-speed devices compared to ESP32)
- Cache –
Connectivity
- 2.4 GHz 802.11 b/g/n Wi-Fi 4 with 40 MHz bandwidth support
- Bluetooth Low Energy (BLE) 5.0 connectivity with long-range support, up to 2Mbps data rate.
Peripherals
- 44x programmable GPIOs (10 more than ESP32)
- SD/MMC host
- SPI, I2C, PWM, UART, RMT (Remote Control), TWAI (Two-Wire Automotive Interface)
- ADC, DAC
- I2S
- USB OTG
- Capacitive touch input
Security
- AES-XTS-based flash encryption
- RSA-based secure boot.
- Digital signature peripheral and an HMAC module (similar to a secure element)
- “World Controller” peripheral that provides two fully-isolated execution environments and enables a trusted-execution environment or a privilege-separation scheme.
Compared to the base ESP32, the ESP32-S3 has a significant hardware security support. These features are similar to the previous single-core ESP32-S3. Security features include an HMAC controller for message authentication. The Digital Signature (DS) module provides hardware-accelerated message signing. Also available is a secure boot capability that verifies the RSA-PSS signature of an application image before executing it. Additional encryption includes "Flash Encryption" for off-chip flash memory. Fully-isolated execution environments are possible with the "World Controller" peripheral. One use of this feature would be to isolate security-sensitive data tasks from the rest of the application.
It appears the initial modules incorporating the chip will come in the form of a WROOM and a new S3-DevKit. More information is available on the ESP32 S-Series SOC's product page.